EP1M350F780C6N vs EP1M350F780I5 Comparison
Detailed side-by-side comparison of EP1M350F780C6N by Intel and EP1M350F780I5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP1M350F780C6N
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N β Last Time BuyAltera
EP1M350F780I5
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndSpecification Comparison
| Parameter | EP1M350F780C6N | EP1M350F780I5 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $219.40 | $178.00 |
| Family | Mercury (EP1M350) | β |
| Device Type | Loadable Programmable Logic Device (PLD) / FPGA | β |
| Logic Family | CMOS, SRAM-based LUT | β |
| System Gates | 350,000 | β |
| Logic Cells / Elements | 14,400 | β |
| User I/Os | 486 | β |
| Integrated Transceivers | Yes, with CDR up to 1.25 Gbps | β |
| Core Supply Voltage | 1.8 V | β |
| Package | 780-ball FC-FBGA (FINE LINE BGA-780) | 780-ball FineLine BGA (F780) |
| Terminal Form | Ball | β |
| Package Code (JEDEC) | S-PBGA-B780 | β |
| Operating Temperature | 0 C to 85 C | β |
| Configuration Interface | JTAG (IEEE 1149.1) / passive serial | β |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: msl_level] | β |
| Lead-Free | [DATA_NEEDED: lead_free] | [DATA_NEEDED: lead-free status] |
| Architecture | Look-up table (LUT)-based, optimized for high-speed serial I/O | β |
| Total Package Pins / Balls | 780 | β |
| Device Family | β | Altera Mercury (EP1M) Enhanced Configuration Device |
| Function | β | FPGA configuration PROM with integrated controller |
| Storage Density Code | β | 350 (high-density) |
| Supported Configuration Schemes | β | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | β | Configuration controller + flash memory array |
| Programming Method | β | In-system programmable via Altera Quartus / JTAG |
| Temperature Grade (suffix "I") | β | Industrial |
| Speed Grade | β | 5 |
| Target FPGA Compatibility | β | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | β | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | β | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | β | Yes |