EP1S10B672C6 vs EP1S10F672C6 Comparison
Detailed side-by-side comparison of EP1S10B672C6 by Intel and EP1S10F672C6 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S10B672C6 | EP1S10F672C6 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $185.00 | $72.00 |
| Manufacturer | Intel / Altera | โ |
| Series | Stratix | Stratixยฎ I |
| Logic Elements / Cells | 10,570 | โ |
| LABs / CLBs | 1,057 | โ |
| User I/Os | 345 | โ |
| Package | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | 672-ball FineLine BGA (FBGA) |
| Supply Voltage (Core) | 1.5 V (1.425 V - 1.575 V) | โ |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Operating Frequency | 450.05 MHz | โ |
| Operating Temperature | 0 C to 85 C (Commercial Extended) | 0C to +85C (Commercial) |
| Logic Family | CMOS | โ |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Supplier Device Package | 672-BGA | โ |
| Memory | Embedded TriMatrix (MRAM/M4K) blocks | โ |
| DSP Blocks | Yes, dedicated multiply-accumulate blocks | 6 |
| Clock Management | PLLs for clock synthesis | โ |
| Configuration | JTAG / passive serial / fast passive parallel | โ |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Family | โ | Stratix FPGA |
| Logic Elements (LE) | โ | 10,570 |
| Logic Array Blocks (LABs) | โ | 1057 |
| Total Memory Bits | โ | 920,448 bits |
| Embedded Memory | โ | TriMatrix (MRAM/M4K) |
| Number of I/Os | โ | 345 |
| Number of PLLs | โ | 12 (6 per device side) |
| Core Voltage | โ | 1.5 V |
| Maximum Core Frequency | โ | 420.17 MHz |
| Configuration Modes | โ | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| JTAG Support | โ | IEEE 1149.1 boundary-scan |