EP1S10B672C7N vs EP1S10B672C6 Comparison
Detailed side-by-side comparison of EP1S10B672C7N by Intel and EP1S10B672C6 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S10B672C7N | EP1S10B672C6 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $67.90 | $185.00 |
| Manufacturer | Intel / Altera | Intel / Altera |
| Product Family | Stratix | β |
| Logic Family | CMOS | CMOS |
| Logic Elements/Cells | 10570 cells | β |
| Maximum Internal Clock | 420.17 MHz | β |
| Core Supply Voltage | 1.5 V | β |
| Technology Node | 130 nm | β |
| Package Code | BGA | β |
| Number of Terminals | 672 | β |
| Package Body Size | 35 x 35 mm | β |
| Ball Pitch | 1.27 mm | β |
| Package Shape | Square | β |
| Temperature Grade | Commercial extended, 0 to 85 C | β |
| Terminal Form | Ball | β |
| Configuration/JTAG | JTAG boundary-scan per Stratix family data sheet | β |
| Number of User I/O in 672-BGA | [DATA_NEEDED: user I/O count] | β |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | β |
| Embedded PLLs | [DATA_NEEDED: PLL count] | β |
| Config Device Compatibility | [DATA_NEEDED: supported configuration devices] | β |
| RoHS | unknown - N suffix may indicate Pb-free, not verified in fetched data | β |
| Series | β | Stratix |
| Logic Elements / Cells | β | 10,570 |
| LABs / CLBs | β | 1,057 |
| User I/Os | β | 345 |
| Package | β | 672-BBGA (35 x 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core) | β | 1.5 V (1.425 V - 1.575 V) |
| Process Technology | β | 130 nm CMOS |
| Maximum Operating Frequency | β | 450.05 MHz |
| Operating Temperature | β | 0 C to 85 C (Commercial Extended) |
| Mounting Type | β | Surface Mount (BGA) |
| Supplier Device Package | β | 672-BGA |
| Memory | β | Embedded TriMatrix (MRAM/M4K) blocks |
| DSP Blocks | β | Yes, dedicated multiply-accumulate blocks |
| Clock Management | β | PLLs for clock synthesis |
| Configuration | β | JTAG / passive serial / fast passive parallel |
| RoHS Status | β | Compliant |