EP1S10F780I6N vs EP1S10F780C5N Comparison
Detailed side-by-side comparison of EP1S10F780I6N by Intel and EP1S10F780C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP1S10F780C5N
EP1S10F780C5N - Stratix 10570 Cells FPGA, 780-FBGA | Intel (Altera)
EP1S10F780C5N β Last Time BuySpecification Comparison
| Parameter | EP1S10F780I6N | EP1S10F780C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $98.75 | $195.00 |
| Family | Stratix | Stratix |
| Logic Elements | 10,570 | 10570 |
| Logic Array Blocks (LABs) | 1,057 | β |
| User I/Os | 426 | β |
| Embedded RAM (Total) | 920,448 bits | β |
| M512 Blocks | 94 (32 x 18 bits each) | β |
| M4K Blocks | 60 (128 x 36 bits each) | β |
| M-RAM Blocks | 1 (4 Kbit) | β |
| PLLs | 6 | [DATA_NEEDED: PLL count] |
| Clock Outputs | 16 | β |
| DSP Blocks | 12 | 12 (per family datasheet) |
| Transceiver Channels | 12 (not populated on I6 speed grade) | β |
| Core Voltage (VCCINT) | 1.5 V | β |
| I/O Voltage (VCCIO) | 1.5 V, 1.8 V, 2.5 V, 3.3 V (per bank) | β |
| Process Technology | 0.13 Β΅m CMOS | 130 nm CMOS |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial) | 0C to +85C (Commercial) |
| Speed Grade | -6 (6.0 ns core clock period) | C5 |
| Package | 780-ball FineLine BGA, 29 x 29 mm, 1.0 mm pitch | 780-ball FBGA (29 x 29 mm, 1 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | 3 (168 hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant (N suffix) |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | Passive Serial, Active Serial, JTAG |
| Logic Family | CMOS | β |
| Supply Voltage Nominal | 1.5 V | β |
| Total RAM Bits | β | 920448 |
| User I/O Count | β | 426 |
| Core Voltage | β | 1.5 V |
| Internal Operating Frequency (max) | β | 500 MHz |
| Number of Logic Array Blocks (LABs) | β | [DATA_NEEDED: LAB count] |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, SSTL, LVDS (per family datasheet) |
| Lead-Free | β | Yes |