EP1S20B672C7N vs EP1S10B672C7N Comparison

Detailed side-by-side comparison of EP1S20B672C7N by Intel and EP1S10B672C7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1S20B672C7N EP1S10B672C7N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $320.00 $67.90
Series Stratix β€”
Family Stratix (original) β€”
Process Technology 0.13 Β΅m CMOS β€”
Logic Elements (LEs) 18,460 β€”
LABs / CLBs 1,846 β€”
Embedded Memory Bits 1,669,248 bits β€”
Maximum User I/O 426 β€”
Number of Pins / Balls 672 β€”
Package Type 672-BBGA (Fine-pitch BGA, 35 Γ— 35 mm, 1.27 mm pitch) β€”
Supply Voltage (Core, VCCINT) 1.5 V β€”
Operating Temperature 0 Β°C to 85 Β°C (Commercial Extended) β€”
Speed Grade -7 β€”
Mounting Type Surface Mount (BGA) β€”
MSL Level 3 (per JEDEC J-STD-020) β€”
Logic Family CMOS CMOS
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
Lead-Free [DATA_NEEDED: lead-free status] β€”
Manufacturer β€” Intel / Altera
Product Family β€” Stratix
Logic Elements/Cells β€” 10570 cells
Maximum Internal Clock β€” 420.17 MHz
Core Supply Voltage β€” 1.5 V
Technology Node β€” 130 nm
Package Code β€” BGA
Number of Terminals β€” 672
Package Body Size β€” 35 x 35 mm
Ball Pitch β€” 1.27 mm
Package Shape β€” Square
Temperature Grade β€” Commercial extended, 0 to 85 C
Terminal Form β€” Ball
Configuration/JTAG β€” JTAG boundary-scan per Stratix family data sheet
Number of User I/O in 672-BGA β€” [DATA_NEEDED: user I/O count]
Total RAM Bits β€” [DATA_NEEDED: total RAM bits]
Embedded PLLs β€” [DATA_NEEDED: PLL count]
Config Device Compatibility β€” [DATA_NEEDED: supported configuration devices]
RoHS β€” unknown - N suffix may indicate Pb-free, not verified in fetched data

Datasheets & Resources

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