EP1S20B672C7N vs EP1S20F672C7 Comparison
Detailed side-by-side comparison of EP1S20B672C7N by Intel and EP1S20F672C7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S20B672C7N | EP1S20F672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $320.00 | $195.00 |
| Series | Stratix | Stratix |
| Family | Stratix (original) | Altera Stratix FPGA |
| Process Technology | 0.13 Β΅m CMOS | β |
| Logic Elements (LEs) | 18,460 | 18,460 |
| LABs / CLBs | 1,846 | β |
| Embedded Memory Bits | 1,669,248 bits | 1,669,248 |
| Maximum User I/O | 426 | β |
| Number of Pins / Balls | 672 | β |
| Package Type | 672-BBGA (Fine-pitch BGA, 35 Γ 35 mm, 1.27 mm pitch) | β |
| Supply Voltage (Core, VCCINT) | 1.5 V | β |
| Operating Temperature | 0 Β°C to 85 Β°C (Commercial Extended) | 0C to 85C (commercial) |
| Speed Grade | -7 | C7 |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| MSL Level | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| Logic Family | CMOS | CMOS, SRAM-based |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| User I/O Pins | β | 426 |
| DSP Blocks | β | [DATA_NEEDED: DSP block count] |
| Package | β | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Core Supply Voltage | β | 1.5 V |
| Configuration Modes | β | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Clock PLLs | β | Up to 10 |