EP1S20F672C7 vs EP1S20B672C7N Comparison
Detailed side-by-side comparison of EP1S20F672C7 by Intel and EP1S20B672C7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S20F672C7 | EP1S20B672C7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $320.00 |
| Series | Stratix | Stratix |
| Family | Altera Stratix FPGA | Stratix (original) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | 1,669,248 bits |
| User I/O Pins | 426 | β |
| DSP Blocks | [DATA_NEEDED: DSP block count] | β |
| Package | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | β |
| Logic Family | CMOS, SRAM-based | CMOS |
| Core Supply Voltage | 1.5 V | β |
| Operating Temperature | 0C to 85C (commercial) | 0 Β°C to 85 Β°C (Commercial Extended) |
| Speed Grade | C7 | -7 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| MSL Level | [DATA_NEEDED: MSL level] | 3 (per JEDEC J-STD-020) |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance] |
| Clock PLLs | Up to 10 | β |
| Process Technology | β | 0.13 Β΅m CMOS |
| LABs / CLBs | β | 1,846 |
| Maximum User I/O | β | 426 |
| Number of Pins / Balls | β | 672 |
| Package Type | β | 672-BBGA (Fine-pitch BGA, 35 Γ 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | β | 1.5 V |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |