EP1S20F672C7 vs EP1S20F672C6 Comparison
Detailed side-by-side comparison of EP1S20F672C7 by Intel and EP1S20F672C6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S20F672C7 | EP1S20F672C6 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $470.00 |
| Series | Stratix | Stratix |
| Family | Altera Stratix FPGA | Stratix (first generation) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | 1,669,248 |
| User I/O Pins | 426 | β |
| DSP Blocks | [DATA_NEEDED: DSP block count] | β |
| Package | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | 672-ball FineLine BGA |
| Logic Family | CMOS, SRAM-based | β |
| Core Supply Voltage | 1.5 V | β |
| Operating Temperature | 0C to 85C (commercial) | 0Β°C to +85Β°C (Commercial) |
| Speed Grade | C7 | C6 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | β |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| Clock PLLs | Up to 10 | β |
| Manufacturer | β | Altera (now Intel) |
| Process Technology | β | 0.13 Β΅m CMOS |
| Logic Array Blocks (LABs) | β | 1,846 |
| Maximum User I/Os | β | 426 |
| Package Code | β | F672 |
| Supply Voltage | β | Core 1.5 V, I/O programmable |