EP1S20F780C6N vs EP1S30F780C6GA Comparison
Detailed side-by-side comparison of EP1S20F780C6N by Intel and EP1S30F780C6GA by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S20F780C6N | EP1S30F780C6GA |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $188.75 | $1,100.00 |
| Family | Stratix | Stratix FPGA |
| Manufacturer | Intel (formerly Altera) | β |
| Process Technology | 130 nm CMOS | 0.13 um |
| Logic Elements (LEs) | 18,460 | β |
| Configurable Logic Blocks (CLBs) | 2,132 | β |
| Embedded Memory Bits | 1,669,248 | β |
| Memory Type | TriMatrix (M512 / M4K / M-RAM blocks) | β |
| DSP Blocks | Embedded 9x9 multiplier blocks | Integrated dedicated multipliers |
| Maximum User I/O Pins | 586 | β |
| Package | 780-ball FC-FBGA (Fine-pitch BGA) | β |
| Package Dimensions | 29 x 29 mm, 1.0 mm pitch | β |
| Core Supply Voltage | 1.5 V | β |
| Operating Temperature | 0 C to +85 C (commercial) | [DATA_NEEDED: industrial/commercial range] |
| Speed Grade | C6 (6 ns pin-to-pin delay class) | β |
| Maximum Internal Frequency | 450.05 MHz | β |
| Lead-Free / RoHS | Yes (lead-free) | β |
| Configuration Methods | PS, PPS, PPA, JTAG via EPC configuration device | β |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL, PCI, PCI-X | β |
| Series | β | Stratix |
| Logic Elements | β | 32,470 |
| Total RAM Bits | β | 3,317,184 |
| Number of I/O | β | 597 (maximum user I/O) |
| Core Voltage | β | 1.425 V to 1.575 V |
| Package / Case | β | 780-BBGA, FCBGA |
| Supplier Device Package | β | 780-FBGA (29 x 29 mm) |
| Mounting Type | β | Surface Mount |
| PLL Count | β | Multiple (per Stratix family) |
| Configuration Memory | β | SRAM-based, volatile |
| RoHS Status | β | [DATA_NEEDED] |
| Lead-Free Status | β | [DATA_NEEDED] |
| MSL Level | β | [DATA_NEEDED] |
| Architecture | β | Altera Stratix (programmable logic + TriMatrix memory + DSP blocks) |