EP1S25F672C7N vs EP1S20F672C7N Comparison

Detailed side-by-side comparison of EP1S25F672C7N by Altera and EP1S20F672C7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1S25F672C7N EP1S20F672C7N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $535.00 $109.20
Device Family Stratix β€”
Logic Elements (LEs) 25,660 18,460
Logic Array Blocks (LABs) 2,566 β€”
Embedded Memory Bits 1,944,576 β€”
Maximum User I/O 473 586
Number of I/O Pins 672 (BGA balls) β€”
Package 672-BBGA (FineLine BGA), 35 Γ— 35 mm, 1.27 mm pitch 672-FBGA (FineLine BGA)
Process Technology 0.13 Β΅m CMOS 130 nm CMOS
Core Supply Voltage (VCCINT) 1.5 V β€”
I/O Supply Voltage (VCCIO) [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] β€”
Operating Temperature 0 Β°C to 85 Β°C (commercial) 0Β°C to +85Β°C (commercial)
Mounting Type Surface Mount Surface Mount
Configuration Method JTAG / Passive Serial / Active Serial β€”
MSL Level [DATA_NEEDED: MSL rating] [DATA_NEEDED: moisture sensitivity level]
RoHS Status [DATA_NEEDED: confirm from product page] β€”
Series β€” Stratix (first generation)
Family β€” Stratix
Logic Cells β€” 18,460
Configurable Logic Blocks (CLBs) β€” 2,132
Embedded Memory (TriMatrix) β€” 1,669,248 bits (426 Kbit total)
DSP Blocks β€” 56 (dedicated 18x18 multipliers)
I/O Banks β€” [DATA_NEEDED: I/O bank count]
PLLs β€” Up to 12
Maximum Operating Frequency β€” 420.17 MHz
Core Voltage β€” 1.5 V
Package Body Size β€” 35 mm x 35 mm
Ball Pitch β€” 1.27 mm
Speed Grade β€” C7 (-7)
Lead-Free / RoHS β€” Yes (lead-free finish, RoHS compliant)
Configuration Modes β€” PS, PPS, FPP, JTAG

Datasheets & Resources

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