EP1S80B956C6AB vs EP1S80B956C5N Comparison
Detailed side-by-side comparison of EP1S80B956C6AB by Intel and EP1S80B956C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S80B956C6AB | EP1S80B956C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $142.00 | $175.00 |
| Family | Stratix | Altera Stratix |
| Logic Elements (LEs) | 79,040 | β |
| Logic Cells | 79,040 | β |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Voltage | 1.5 V | β |
| Maximum Operating Frequency | 450.05 MHz | β |
| User I/O Pins | 683 | β |
| Package | 956-ball FCBGA | 956-ball FCBGA |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 Β°C to +85 Β°C (commercial, 'C' grade) |
| Memory Blocks | TriMatrix embedded RAM | β |
| DSP Blocks | Embedded DSP blocks (per Stratix family) | Yes (dedicated hardware multipliers) |
| PLLs | Multiple PLLs for clock management | Yes (multiple) |
| Configuration Method | SRAM-based, configured via JTAG or passive/active serial | β |
| Manufacturer | Intel (formerly Altera) | β |
| Logic Elements | β | 79,040 |
| Maximum Internal Clock Frequency | β | 500 MHz |
| Core Supply Voltage | β | 1.5 V |
| Speed Grade | β | 5 |
| Memory Architecture | β | TriMatrix on-chip memory |
| I/O Standard Support | β | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per Stratix family) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |