EP1SGX10DF672C5N vs EP1S25F672C5N Comparison

Detailed side-by-side comparison of EP1SGX10DF672C5N by Intel and EP1S25F672C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP1SGX10DF672C5N EP1SGX10DF672C5N - Stratix GX FPGA, 10,570 Cells, 672-BGA | Intel

EP1SGX10DF672C5N - Stratix GX FPGA, 10,570 Cells, 672-BGA | Intel

EP1SGX10DF672C5N ⚠ Last Time Buy

Specification Comparison

Parameter EP1SGX10DF672C5N EP1S25F672C5N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $192.00 $142.00
Family Stratix GX Stratix
Logic Cells 10,570 β€”
Logic Array Blocks (LABs) 1,057 β€”
Configurable Logic Blocks 1,200 β€”
User I/Os 362 β€”
On-chip RAM 920,448 bits β€”
Supply Voltage (Core, VCCINT) 1.5 V nominal (1.425 V to 1.575 V) β€”
Technology 130 nm CMOS β€”
Operating Temperature 0 C to 85 C (Commercial) β€”
Package 672-ball FC-FBGA (FineLine BGA), 33 x 33 mm, 1.0 mm pitch β€”
Mounting Type Surface Mount (Flip-Chip BGA) Surface Mount (BGA)
Logic Family CMOS β€”
Configuration Passive Serial / Passive Parallel / JTAG / Altera Serial β€”
RoHS Status Compliant (FBGA package) Compliant
High-Speed Transceivers Embedded GX transceivers (data rate not specified in provided data [DATA_NEEDED: transceiver count and max data rate]) β€”
Series β€” EP1S25
Logic Elements (Cells) β€” 25,660
Number of CLBs β€” 2,566
Number of Logic Cells / Gates β€” [DATA_NEEDED: total system gates]
Process Technology β€” 130 nm CMOS
Maximum Internal Frequency β€” 500 MHz
Core Supply Voltage β€” 1.5 V (nominal)
Number of I/O Pins β€” 473 user I/O
Number of I/O Banks β€” [DATA_NEEDED: I/O bank count]
Package Type β€” FineLine BGA (FBGA)
Package Pin Count β€” 672
Ball Pitch β€” 1.00 mm
Operating Temperature Range β€” 0 Β°C to +85 Β°C (commercial)
Speed Grade β€” C5
Lead-Free (Pb-Free) β€” Yes (suffix "N")
Configuration Method β€” SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel

Datasheets & Resources

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