EP1SGX25DF800I6N vs EP1SGX25DF800C5N Comparison
Detailed side-by-side comparison of EP1SGX25DF800I6N by Intel and EP1SGX25DF800C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP1SGX25DF800I6N - Stratix GX FPGA, 25K LE, 20x 3.1875 Gbps Transceivers | Intel / Altera
EP1SGX25DF800I6N β Last Time Buy
Specification Comparison
| Parameter | EP1SGX25DF800I6N | EP1SGX25DF800C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,450.00 | $158.00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | [DATA_NEEDED: logic element count] | β |
| Transceiver Channels | 4 to 20 channels | 8 (full-duplex) |
| Maximum Transceiver Data Rate | 3.1875 Gbps per channel | 3.1875 Gbps per channel |
| CDR / SERDES | Embedded clock-data recovery and SERDES | β |
| Memory | TriMatrix memory, up to 2 Mbits | β |
| DSP Blocks | Up to 22 DSP blocks | Embedded multiplier blocks (family-wide) |
| Hard IP | PCI Express PHY, external memory interfaces (DDR, DDR-II, QDR-II, RLDRAM-II) | β |
| Source-Synchronous Channels | 8 channels | β |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | β |
| Package | 800-pin FineLine BGA (DF800) | FBGA-800 (FineLine BGA, 31x31 mm) |
| Speed Grade | -6 (production grade) | C5 (commercial) |
| Temperature Range | Industrial -40C to +100C | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Protocol Support | Gigabit Ethernet, SONET/SDH, PCI Express, custom serial | β |
| Device Logic Elements | β | 25,660 (typical) |
| Process Technology | β | 130 nm |
| Supply Voltage (Core) | β | 1.5 V typical |
| Operating Temperature | β | 0C to +85C (commercial) |
| Lead-Free / RoHS Status | β | Lead-free (N suffix) |
| On-Chip Memory (TriMatrix) | β | Approx. 2 Mbits total |
| PLLs | β | Up to 40 (device-wide) |
| Embedded 8b/10b Encoder/Decoder | β | Yes (one per transceiver channel) |
| PCI Express Hard IP | β | x1, x4 endpoints supported |
| Mounting Type | β | Surface Mount (BGA) |
| MSL Level | β | [DATA_NEEDED: MSL Level] |
| Development Software | β | Quartus II (legacy) |