EP20K1000CF33I8N vs EP20K1000CF33C9ES Comparison
Detailed side-by-side comparison of EP20K1000CF33I8N by Altera and EP20K1000CF33C9ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA
EP20K1000CF33C9ES β Last Time BuySpecification Comparison
| Parameter | EP20K1000CF33I8N | EP20K1000CF33C9ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $210.00 | $215.00 |
| Family | APEX 20KC | APEX-20KC |
| Logic Elements | 38,400 cells | 38,400 |
| System Gates | 1,000,000 (approx.) | β |
| Maximum Internal Clock Frequency | 301.21 MHz | β |
| Propagation Delay | 1.79 ns | β |
| Number of Logic Elements / Cells | 38,400 | β |
| Process Technology | 0.15 Β΅m CMOS | 0.18 um CMOS |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | β |
| Number of I/O Pins | 700 user I/O | β |
| Number of Pins | 1020 | β |
| Package Type | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) | β |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial) | 0 C to +85 C (commercial) |
| Embedded Memory | Dual-port RAM via ESB blocks | β |
| PLL Count | 4 | β |
| Configuration Interface | IEEE 1149.1 JTAG, EPC serial/parallel | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | I8 | C9 |
| Manufacturer | β | Intel (formerly Altera) |
| Typical Gate Count | β | 1,000,000 system gates |
| Logic Array Blocks (LABs) | β | 3,840 |
| Embedded System Blocks (ESBs) | β | 212 |
| Total Embedded RAM Bits | β | 327,680 bits |
| Maximum User I/O Pins | β | 708 |
| Package | β | 1,020-ball FineLine BGA (FBGA) |
| Logic Element Architecture | β | 4-input LUT with dedicated carry chain |
| Maximum Embedded RAM per ESB | β | 32,768 bits (dual-port, FIFO support) |
| Phase-Locked Loops | β | Up to 4 enhanced PLLs |
| MultiVolt I/O Support | β | 1.8V / 2.5V / 3.3V / 5.0V |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| Configuration Method | β | Passive serial / Passive parallel / JTAG |
| Lead-Free | β | [DATA_NEEDED: lead-free finish status] |