EP20K1000CF33I8N vs EP20K1500CF33C8ES Comparison
Detailed side-by-side comparison of EP20K1000CF33I8N by Altera and EP20K1500CF33C8ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K1000CF33I8N | EP20K1500CF33C8ES |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $210.00 | $288.00 |
| Family | APEX 20KC | β |
| Logic Elements | 38,400 cells | 51,840 |
| System Gates | 1,000,000 (approx.) | 1,500,000 |
| Maximum Internal Clock Frequency | 301.21 MHz | β |
| Propagation Delay | 1.79 ns | β |
| Number of Logic Elements / Cells | 38,400 | β |
| Process Technology | 0.15 Β΅m CMOS | β |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | β |
| Number of I/O Pins | 700 user I/O | β |
| Number of Pins | 1020 | β |
| Package Type | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) | β |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial) | [DATA_NEEDED: operating temperature range] |
| Embedded Memory | Dual-port RAM via ESB blocks | β |
| PLL Count | 4 | β |
| Configuration Interface | IEEE 1149.1 JTAG, EPC serial/parallel | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance for ES variant] |
| Speed Grade | I8 | -1 (C8) |
| Series | β | APEX 20K (APEX 20KE family) |
| Manufacturer | β | Intel (formerly Altera) |
| Maximum Gates (Equivalent) | β | 2,392,000 |
| Embedded System Block (ESB) Bits | β | 442,368 |
| CAM Bits | β | 216 Kbit |
| Number of PLLs | β | 4 |
| Number of Clocks | β | 8 clock pins |
| Maximum User I/O | β | 808 (1020-FBGA) |
| Package | β | 1020-FBGA (FCBGA), 33x33 mm |
| Voltage - Supply (Core) | β | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) |
| I/O Standard Support | β | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Programming Interface | β | ByteBlaster / MasterBlaster / Altera USB-Blaster |
| Sample Tier | β | ES (engineering sample) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |