EP20K1000CF672C7GZ vs EP20K1000CF33C9ES Comparison
Detailed side-by-side comparison of EP20K1000CF672C7GZ by Intel and EP20K1000CF33C9ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA
EP20K1000CF33C9ES โ Last Time BuySpecification Comparison
| Parameter | EP20K1000CF672C7GZ | EP20K1000CF33C9ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.40 | $215.00 |
| Family | APEX 20KC | APEX-20KC |
| Series | APEX-20KCยฎ | โ |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| System Gates | 1,000,000 | โ |
| Logic Elements / Cells | 38,400 | โ |
| Total RAM Bits | 327,680 | โ |
| Number of I/O | 508 | โ |
| Number of LABs/CLBs | 2560 | โ |
| Number of EABs | 160 | โ |
| Number of Logic Elements per EAB | 2048 bits | โ |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | โ |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | โ |
| Package / Case | 672-FBGA (672-BBGA) | โ |
| Supplier Device Package | 672-FBGA (27x27 mm, 1.27 mm pitch) | โ |
| Mounting Type | Surface Mount | โ |
| Speed Grade | C7 (7 ns pin-to-pin delay, commercial) | C9 |
| Operating Temperature | 0ยฐC to +85ยฐC | 0 C to +85 C (commercial) |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | Yes | โ |
| Process Technology | 0.15 ยตm CMOS | 0.18 um CMOS |
| Typical Gate Count | โ | 1,000,000 system gates |
| Logic Elements | โ | 38,400 |
| Logic Array Blocks (LABs) | โ | 3,840 |
| Embedded System Blocks (ESBs) | โ | 212 |
| Total Embedded RAM Bits | โ | 327,680 bits |
| Maximum User I/O Pins | โ | 708 |
| Package | โ | 1,020-ball FineLine BGA (FBGA) |
| Logic Element Architecture | โ | 4-input LUT with dedicated carry chain |
| Maximum Embedded RAM per ESB | โ | 32,768 bits (dual-port, FIFO support) |
| Phase-Locked Loops | โ | Up to 4 enhanced PLLs |
| MultiVolt I/O Support | โ | 1.8V / 2.5V / 3.3V / 5.0V |
| JTAG Support | โ | IEEE 1149.1 boundary-scan |
| Configuration Method | โ | Passive serial / Passive parallel / JTAG |
| Lead-Free | โ | [DATA_NEEDED: lead-free finish status] |