EP20K100CQ208C8 vs EP20K100EQC208-1X Comparison
Detailed side-by-side comparison of EP20K100CQ208C8 by Altera and EP20K100EQC208-1X by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K100CQ208C8
EP20K100CQ208C8 - APEX20KE FPGA 100K Gates 208-PQFP | Altera
EP20K100CQ208C8 ObsoleteIntel
EP20K100EQC208-1X
EP20K100EQC208-1X - 100K APEX-20KE FPGA, 151 I/O | Intel
EP20K100EQC208-1X ObsoleteSpecification Comparison
| Parameter | EP20K100CQ208C8 | EP20K100EQC208-1X |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.40 | $152.00 |
| Series | APEX 20KE | β |
| Logic Elements | 4,160 | 4,160 |
| Typical Gates | 100,000 | β |
| Maximum System Gates | 263,000 | β |
| Embedded System Block (ESB) Bits | 53,248 | β |
| Dedicated RAM Bits | 100,000 | β |
| Number of PLLs | 4 | β |
| User I/O Pins | 208 | β |
| Package | 208-PQFP (28x28 mm) | 208-pin PQFP (EQC208) |
| Speed Grade | C8 | -1 (standard) |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C |
| Supply Voltage Core | 1.8 V | β |
| I/O Standard Support | 1.8V / 2.5V / 3.3V / 5.0V LVTTL/LVCMOS, 3.3V PCI | β |
| Configuration Modes | Passive Serial, Passive Parallel Synchronous, Passive Parallel Asynchronous, Boundary-Scan JTAG | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Lead-free (Pb-free), RoHS compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Family | β | APEX-20KE |
| Typical Gate Count | β | 100,000 gates |
| Embedded Memory (bits) | β | 53,248 |
| Embedded System Blocks (ESBs) | β | 26 |
| Maximum User I/O | β | 151 |
| Process Technology | β | 0.15 micrometer CMOS, all-layer copper |
| Propagation Delay | β | 1.6 ns |
| Core Supply Voltage | β | 1.8 V |
| MultiVolt I/O Support | β | 1.8V / 2.5V / 3.3V / 5.0V |
| PLLs | β | 4 |
| Configuration Interface | β | JTAG (IEEE 1149.1), passive serial/parallel |
| MSL Level | β | 3 (168 Hours) |