EP20K100CQ208C8ES vs EP20K100CQ208C8 Comparison

Detailed side-by-side comparison of EP20K100CQ208C8ES by Intel and EP20K100CQ208C8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP20K100CQ208C8ES

EP20K100CQ208C8ES - APEX 20K FPGA 4160 LE | Intel

EP20K100CQ208C8ES Obsolete
Altera
EP20K100CQ208C8

EP20K100CQ208C8 - APEX20KE FPGA 100K Gates 208-PQFP | Altera

EP20K100CQ208C8 Obsolete

Specification Comparison

Parameter EP20K100CQ208C8ES EP20K100CQ208C8
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $13.40
Logic Elements/Cells 4160 β€”
Number of User I/O 159 β€”
Package / Case 208-pin QFP (BFQFP) β€”
Mounting Type Surface Mount Surface Mount
Packaging Tray β€”
Moisture Sensitivity Level 3 (168 hours) β€”
Core Supply Voltage [DATA_NEEDED: core supply voltage] β€”
I/O Supply Voltage [DATA_NEEDED: I/O supply voltage] β€”
Maximum System Gates [DATA_NEEDED: maximum system gates] 263,000
Embedded RAM Bits [DATA_NEEDED: embedded RAM bits] β€”
Speed Grade [DATA_NEEDED: speed grade from ordering code] C8
Operating Temperature Range [DATA_NEEDED: commercial temperature grade] β€”
Configuration Type [DATA_NEEDED: configuration type] β€”
Compatible Configuration Devices [DATA_NEEDED: recommended configuration devices] β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free Finish [DATA_NEEDED: lead-free status] β€”
Lifecycle Status Obsolete β€”
Series β€” APEX 20KE
Logic Elements β€” 4,160
Typical Gates β€” 100,000
Embedded System Block (ESB) Bits β€” 53,248
Dedicated RAM Bits β€” 100,000
Number of PLLs β€” 4
User I/O Pins β€” 208
Package β€” 208-PQFP (28x28 mm)
Operating Temperature β€” 0C to +85C (Commercial)
Supply Voltage Core β€” 1.8 V
I/O Standard Support β€” 1.8V / 2.5V / 3.3V / 5.0V LVTTL/LVCMOS, 3.3V PCI
Configuration Modes β€” Passive Serial, Passive Parallel Synchronous, Passive Parallel Asynchronous, Boundary-Scan JTAG
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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