EP20K100EBC356-3N vs EP20K100EBC652-2X Comparison
Detailed side-by-side comparison of EP20K100EBC356-3N by Altera and EP20K100EBC652-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K100EBC356-3N | EP20K100EBC652-2X |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $85.00 |
| Series | APEX-20KE | β |
| Family | APEX 20K | APEX 20KE |
| Logic Elements / Cells | 4160 | β |
| System Gates | 100,000 | β |
| Embedded Memory (bits) | 53,248 | β |
| Embedded System Blocks (ESBs) | 26 | 26 |
| Maximum User I/Os | 246 | β |
| Number of Pins | 356 | β |
| Package | 356-LBGA (Ball Grid Array) | 652-ball BGA (EBC652) |
| Package Dimensions | 45 x 45 mm | β |
| Ball Pitch | 1.27 mm | β |
| Process Technology | 0.22 Β΅m CMOS | 0.18 Β΅m CMOS, SRAM-based |
| Core Supply Voltage | 1.8 V | β |
| Propagation Delay | 1.6 ns (speed grade -3N) | β |
| Maximum Internal Frequency | 250 MHz | β |
| Operating Temperature | 0 Β°C to +85 Β°C | 0C to +85C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Programmable Interface | JTAG (IEEE 1149.1) | β |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | β |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Typical Gates | β | 100,000 |
| Maximum System Gates | β | 263,000 |
| Logic Elements | β | 4,160 |
| Maximum RAM Bits | β | 53,248 |
| Maximum User I/O Pins | β | 246 |
| Supply Voltage - Core | β | 1.8 V |
| Supply Voltage - I/O | β | 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | β | -2 (faster commercial) |
| Configuration Method | β | Passive Serial / Passive Parallel / JTAG (EPC) |
| Clock Resources | β | Up to 4 DLLs, multiple global clocks |