EP20K100EBC652-2X vs EP20K1000EBC652-2X Comparison

Detailed side-by-side comparison of EP20K100EBC652-2X by Altera and EP20K1000EBC652-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K100EBC652-2X EP20K1000EBC652-2X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $85.00 $99.00
Family APEX 20KE APEX-20KE
Typical Gates 100,000 1,000,000 system gates
Maximum System Gates 263,000 β€”
Logic Elements 4,160 β€”
Embedded System Blocks (ESBs) 26 β€”
Maximum RAM Bits 53,248 β€”
Maximum User I/O Pins 246 β€”
Supply Voltage - Core 1.8 V β€”
Supply Voltage - I/O 1.8 V / 2.5 V / 3.3 V β€”
Package 652-ball BGA (EBC652) 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch)
Speed Grade -2 (faster commercial) β€”
Process Technology 0.18 Β΅m CMOS, SRAM-based 0.22 Β΅m (some sources 0.15 Β΅m) all-layer copper-metal CMOS
Operating Temperature 0C to +85C (commercial) 0 Β°C to +85 Β°C (commercial)
Mounting Type Surface Mount Surface Mount
Configuration Method Passive Serial / Passive Parallel / JTAG (EPC) β€”
Clock Resources Up to 4 DLLs, multiple global clocks β€”
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Device Logic Elements β€” 38,400
Embedded Memory Bits β€” 327,680 bits
User I/O Pins β€” 488
Maximum User I/O β€” 488
Propagation Delay β€” 1.6 ns
Internal Maximum Frequency β€” 350 MHz
Logic Blocks / Macros β€” 2,560 macros
PLLs β€” 4
Core Voltage β€” 1.8 V
Configuration Interface β€” JTAG (IEEE 1149.1), Passive Serial, Altera configuration

Datasheets & Resources

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