EP20K100EBC652-2X vs EP20K100EBC356-3N Comparison
Detailed side-by-side comparison of EP20K100EBC652-2X by Altera and EP20K100EBC356-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K100EBC652-2X | EP20K100EBC356-3N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $85.00 | $92.00 |
| Family | APEX 20KE | APEX 20K |
| Typical Gates | 100,000 | β |
| Maximum System Gates | 263,000 | β |
| Logic Elements | 4,160 | β |
| Embedded System Blocks (ESBs) | 26 | 26 |
| Maximum RAM Bits | 53,248 | β |
| Maximum User I/O Pins | 246 | β |
| Supply Voltage - Core | 1.8 V | β |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | β |
| Package | 652-ball BGA (EBC652) | 356-LBGA (Ball Grid Array) |
| Speed Grade | -2 (faster commercial) | β |
| Process Technology | 0.18 Β΅m CMOS, SRAM-based | 0.22 Β΅m CMOS |
| Operating Temperature | 0C to +85C (commercial) | 0 Β°C to +85 Β°C |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | β |
| Clock Resources | Up to 4 DLLs, multiple global clocks | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Series | β | APEX-20KE |
| Logic Elements / Cells | β | 4160 |
| System Gates | β | 100,000 |
| Embedded Memory (bits) | β | 53,248 |
| Maximum User I/Os | β | 246 |
| Number of Pins | β | 356 |
| Package Dimensions | β | 45 x 45 mm |
| Ball Pitch | β | 1.27 mm |
| Core Supply Voltage | β | 1.8 V |
| Propagation Delay | β | 1.6 ns (speed grade -3N) |
| Maximum Internal Frequency | β | 250 MHz |
| Programmable Interface | β | JTAG (IEEE 1149.1) |
| I/O Standards Supported | β | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ |