EP20K100QC240-3N vs EP20K100QC240-3 Comparison

Detailed side-by-side comparison of EP20K100QC240-3N by Altera and EP20K100QC240-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 βœ“ Active

Specification Comparison

Parameter EP20K100QC240-3N EP20K100QC240-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $24.50
Device Type FPGA β€”
Family APEX-20K β€”
Gate Count 100000 gates β€”
Logic Cells 4160 cells β€”
User I/O 189 I/O β€”
Distributed Memory 53248 bits β€”
Macrocells 416 macrocells β€”
Supply Voltage 2.375 V to 2.625 V β€”
Nominal Supply 2.5 V β€”
Maximum Frequency 167 MHz β€”
Operating Temperature 0 C to 85 C β€”
Package 240-BFQFP β€”
Pin Count 240 pins β€”
Mounting Type Surface Mount Surface Mount
Fabrication Process 0.15 um all-layer copper-metal process β€”
Package Pitch 1.27 mm β€”
Package Dimensions 45 mm x 45 mm β€”
RoHS Status unknown β€”
AEC-Q100 not_qualified β€”
Manufacturer β€” Altera
FPGA Family β€” APEX-20K
Number of Logic Elements β€” 4160 cells
Total RAM Bits β€” 53248 bits
Number of User I/O β€” 189
Typical Gate Count β€” 263000 gates
Core Supply Voltage β€” 2.5 V
Maximum Clock Frequency β€” 167 MHz (family rating)
Speed Grade β€” -3
Technology Process β€” 0.22 um
Package Type β€” 240-BFQFP
Number of Pins β€” 240
Operating Temperature Range β€” 0 Β°C to +85 Β°C (commercial)
Propagation Delay β€” [DATA_NEEDED: propagation delay timing table]
Supported I/O Standards β€” [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface β€” [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance β€” [DATA_NEEDED: RoHS compliance for non-N version]

Datasheets & Resources

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