EP20K160EQC240-3 vs EP20K160EQC240-2 Comparison
Detailed side-by-side comparison of EP20K160EQC240-3 by Intel and EP20K160EQC240-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K160EQC240-3
EP20K160EQC240-3 - APEX 20K 160K Gates FPGA | Intel / Altera
EP20K160EQC240-3 ObsoleteIntel
EP20K160EQC240-2
EP20K160EQC240-2 - APEX 20KE 160K Gates FPGA | Intel | QFP-240
EP20K160EQC240-2 ObsoleteSpecification Comparison
| Parameter | EP20K160EQC240-3 | EP20K160EQC240-2 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $98.75 | $108.50 |
| Family | APEX 20K | APEX 20KE |
| Series | EP20K160E | β |
| Typical Gates | 160,000 | 160,000 |
| Maximum System Gates | 404,000 | β |
| Macrocells | 640 | β |
| Logic Elements | 4,160 | β |
| Embedded RAM Bits | 53,248 | β |
| User I/O Pins | 175 | β |
| Package | 240-pin PowerQuad Flat Pack (BQFP / FQFP) | PQFP-240 (QFP-240, FQFP) |
| Core Voltage | 1.8 V | β |
| I/O Voltage | 1.8 V / 2.5 V / 3.3 V (multi-voltage I/O banks) | β |
| Speed Grade | -3 (slowest commercial grade) | -2 |
| Process Technology | 0.18 Β΅m CMOS | 0.18-micron SRAM CMOS |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | 0 C to 85 C (Commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE Std. 1149.1 boundary-scan |
| Configuration Interface | Passive Serial, JTAG | β |
| Mounting Type | Surface Mount (gull-wing QFP) | Surface Mount (Gull Wing) |
| RoHS Status | unknown | Non-compliant (original Altera-era PQFP) |
| Logic Elements (LEs) | β | 6,400 |
| Embedded System Blocks (ESBs) | β | 64 |
| Maximum Embedded Memory | β | 56 Kbits (approx. 7 Kbytes usable) |
| Maximum User I/O (this package) | β | 175 |
| Maximum User I/O (largest package) | β | 271 |
| PLLs | β | 4 |
| Internal Frequency (max) | β | 160 MHz |
| Propagation Delay | β | 1.55 ns |
| Logic Family | β | CMOS |
| Pin Count | β | 240 |
| Supply Voltage (core) | β | [DATA_NEEDED: core VCC value] |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS |
| Configuration Modes | β | Passive Serial, Passive Parallel Synchronous, JTAG |
| MultiCore Architecture | β | Yes (Logic + ESB + I/O) |
| 5.0 V Tolerance | β | Achievable with external resistor |