EP20K200CB652C7ES vs EP20K200EBC652-3N Comparison
Detailed side-by-side comparison of EP20K200CB652C7ES by Altera and EP20K200EBC652-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200CB652C7ES - APEX 20K 200K FPGA 652-BGA | Altera/Intel
EP20K200CB652C7ES โ Last Time BuySpecification Comparison
| Parameter | EP20K200CB652C7ES | EP20K200EBC652-3N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $275.00 | $220.00 |
| Family | APEX 20K | โ |
| Logic Elements | 8,320 | โ |
| Embedded System Block (ESB) RAM | 106,496 bits | โ |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for 652-BGA] | โ |
| Core Voltage (VCCINT) | 1.8 V | โ |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | โ |
| Speed Grade | -7 | -3 (slowest in APEX 20KE family) |
| Operating Temperature (Commercial) | 0 ยฐC to +85 ยฐC | โ |
| Package | 652-BGA | 652-ball BGA |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Method | SRAM (volatile, requires external PROM on power-up) | โ |
| PLL Count | Up to 8 | โ |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS | โ |
| JTAG (IEEE 1149.1) | Yes (boundary-scan) | โ |
| Configuration Device Compatibility | EPC2, EPC8, EPC16, EPC64, microprocessor | โ |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| MSL Level | [DATA_NEEDED: moisture sensitivity level] | โ |
| Series | โ | APEX 20KE (APEX-20KEยฎ) |
| Device Family | โ | EP20K200 |
| System Gates | โ | 200,000 |
| Logic Elements / Cells | โ | 8,320 |
| Logic Array Blocks (LABs) | โ | 832 |
| Macrocells | โ | 832 |
| Embedded RAM | โ | 106,496 bits |
| User I/Os (DigiKey listing) | โ | 376 |
| User I/Os (digchip listing) | โ | 277 |
| Propagation Delay | โ | 2.33 ns |
| Internal Frequency (max) | โ | 189 MHz |
| Process Technology | โ | 0.22 ยตm CMOS |
| Core Supply Voltage | โ | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply (LVDS-capable) | โ | LVDS, 2.5 V referenced (per source variant) |
| Operating Temperature (TJ) | โ | 0 ยฐC to 85 ยฐC (commercial) |
| Configuration | โ | JTAG (IEEE 1149.1), Passive Serial |