EP20K200CF484C8ES vs EP20K200CF484C9N Comparison
Detailed side-by-side comparison of EP20K200CF484C8ES by Altera and EP20K200CF484C9N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K200CF484C8ES | EP20K200CF484C9N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $89.00 | $201.04 |
| Series | APEX-20KC | β |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 8,320 | 8,320 |
| System Gates | 200,000 | β |
| Embedded Memory (RAM bits) | 106,496 | β |
| Number of Logic Array Blocks (LABs) | 104 | β |
| Number of Embedded System Blocks (ESBs) | 13 | β |
| User I/O Pins (max) | 376 | β |
| PLLs | 4 | β |
| Core Voltage | 1.8 V | β |
| Speed Grade | C8 (-8 commercial) | C9 (250 MHz) |
| Package | 484-pin FBGA (FineLine BGA) | 484-pin FineLine BGA (FBGA) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature | 0C to +85C (commercial) | β |
| Process Node | 0.18 micron CMOS | β |
| Configuration Interface | JTAG (IEEE 1149.1) / Altera serial | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP | β |
| Lead Free / RoHS | [DATA_NEEDED: lead-free status] | β |
| Device Type | β | FPGA (Field-Programmable Gate Array) |
| Typical Gates | β | 200,000 |
| Embedded System Block (ESB) Bits | β | 106,496 |
| Maximum User I/O | β | 376 |
| Maximum Clock Frequency | β | 250 MHz |
| Process Technology | β | 0.15 um CMOS |
| Core Supply Voltage (VCCINT) | β | 1.8 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Temperature Grade | β | Industrial (0C to +85C) |
| Configuration Scheme | β | SRAM-based, supports passive serial/parallel and JTAG |
| MSL Level | β | 3 (per JEDEC J-STD-020) |
| RoHS Status | β | Compliant |