EP20K200EBC652-2X vs EP20K200EBC652-3N Comparison
Detailed side-by-side comparison of EP20K200EBC652-2X by Altera and EP20K200EBC652-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K200EBC652-2X | EP20K200EBC652-3N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $220.00 |
| Series | APEX-20KEยฎ | APEX 20KE (APEX-20KEยฎ) |
| Family | APEX-20KE | โ |
| Device Logic Elements | 8,320 | โ |
| Number of LABs/CLBs | 832 | โ |
| Total RAM Bits | 106,496 | โ |
| Number of I/O Pins | 376 | โ |
| Number of Gates | 200,000 (typical) | โ |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 1.71 V to 1.89 V (nominal 1.8 V) |
| Operating Temperature (TJ) | 0C to +85C | 0 ยฐC to 85 ยฐC (commercial) |
| Package | 652-BGA | 652-ball BGA |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | 0.18 um CMOS | 0.22 ยตm CMOS |
| I/O Standard Support | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL | โ |
| Configuration Method | Serial or Parallel PROM, JTAG (IEEE 1149.1) | โ |
| Lead-Free / RoHS | Compliant (per DigiKey listing) | โ |
| Device Family | โ | EP20K200 |
| System Gates | โ | 200,000 |
| Logic Elements / Cells | โ | 8,320 |
| Logic Array Blocks (LABs) | โ | 832 |
| Macrocells | โ | 832 |
| Embedded RAM | โ | 106,496 bits |
| User I/Os (DigiKey listing) | โ | 376 |
| User I/Os (digchip listing) | โ | 277 |
| Propagation Delay | โ | 2.33 ns |
| Internal Frequency (max) | โ | 189 MHz |
| I/O Supply (LVDS-capable) | โ | LVDS, 2.5 V referenced (per source variant) |
| Speed Grade | โ | -3 (slowest in APEX 20KE family) |
| Configuration | โ | JTAG (IEEE 1149.1), Passive Serial |
| RoHS Status | โ | Compliant |