EP20K200EBC652-3N vs EP20K200CB652C7ES Comparison
Detailed side-by-side comparison of EP20K200EBC652-3N by Altera and EP20K200CB652C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200EBC652-3N
EP20K200EBC652-3N - APEX 20KE 200K FPGA, 652-BGA | Altera
EP20K200EBC652-3N ObsoleteAltera
EP20K200CB652C7ES
EP20K200CB652C7ES - APEX 20K 200K FPGA 652-BGA | Altera/Intel
EP20K200CB652C7ES โ Last Time BuySpecification Comparison
| Parameter | EP20K200EBC652-3N | EP20K200CB652C7ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $220.00 | $275.00 |
| Series | APEX 20KE (APEX-20KEยฎ) | โ |
| Device Family | EP20K200 | โ |
| System Gates | 200,000 | โ |
| Logic Elements / Cells | 8,320 | โ |
| Logic Array Blocks (LABs) | 832 | โ |
| Macrocells | 832 | โ |
| Embedded RAM | 106,496 bits | โ |
| User I/Os (DigiKey listing) | 376 | โ |
| User I/Os (digchip listing) | 277 | โ |
| Propagation Delay | 2.33 ns | โ |
| Internal Frequency (max) | 189 MHz | โ |
| Process Technology | 0.22 ยตm CMOS | โ |
| Core Supply Voltage | 1.71 V to 1.89 V (nominal 1.8 V) | โ |
| I/O Supply (LVDS-capable) | LVDS, 2.5 V referenced (per source variant) | โ |
| Package | 652-ball BGA | 652-BGA |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature (TJ) | 0 ยฐC to 85 ยฐC (commercial) | โ |
| Speed Grade | -3 (slowest in APEX 20KE family) | -7 |
| Configuration | JTAG (IEEE 1149.1), Passive Serial | โ |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Family | โ | APEX 20K |
| Logic Elements | โ | 8,320 |
| Embedded System Block (ESB) RAM | โ | 106,496 bits |
| Maximum User I/O Pins | โ | [DATA_NEEDED: maximum user I/O count for 652-BGA] |
| Core Voltage (VCCINT) | โ | 1.8 V |
| I/O Voltage (VCCIO) | โ | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Operating Temperature (Commercial) | โ | 0 ยฐC to +85 ยฐC |
| Configuration Method | โ | SRAM (volatile, requires external PROM on power-up) |
| PLL Count | โ | Up to 8 |
| Supported I/O Standards | โ | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS |
| JTAG (IEEE 1149.1) | โ | Yes (boundary-scan) |
| Configuration Device Compatibility | โ | EPC2, EPC8, EPC16, EPC64, microprocessor |
| MSL Level | โ | [DATA_NEEDED: moisture sensitivity level] |