EP20K200EBC652-3N vs EP20K200EBC652-2X Comparison
Detailed side-by-side comparison of EP20K200EBC652-3N by Altera and EP20K200EBC652-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200EBC652-3N
EP20K200EBC652-3N - APEX 20KE 200K FPGA, 652-BGA | Altera
EP20K200EBC652-3N ObsoleteAltera
EP20K200EBC652-2X
EP20K200EBC652-2X - 8320 LEs APEX-20KE FPGA 652-BGA | Altera
EP20K200EBC652-2X NrndSpecification Comparison
| Parameter | EP20K200EBC652-3N | EP20K200EBC652-2X |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $220.00 | $195.00 |
| Series | APEX 20KE (APEX-20KEยฎ) | APEX-20KEยฎ |
| Device Family | EP20K200 | โ |
| System Gates | 200,000 | โ |
| Logic Elements / Cells | 8,320 | โ |
| Logic Array Blocks (LABs) | 832 | โ |
| Macrocells | 832 | โ |
| Embedded RAM | 106,496 bits | โ |
| User I/Os (DigiKey listing) | 376 | โ |
| User I/Os (digchip listing) | 277 | โ |
| Propagation Delay | 2.33 ns | โ |
| Internal Frequency (max) | 189 MHz | โ |
| Process Technology | 0.22 ยตm CMOS | 0.18 um CMOS |
| Core Supply Voltage | 1.71 V to 1.89 V (nominal 1.8 V) | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Supply (LVDS-capable) | LVDS, 2.5 V referenced (per source variant) | โ |
| Package | 652-ball BGA | 652-BGA |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature (TJ) | 0 ยฐC to 85 ยฐC (commercial) | 0C to +85C |
| Speed Grade | -3 (slowest in APEX 20KE family) | โ |
| Configuration | JTAG (IEEE 1149.1), Passive Serial | โ |
| RoHS Status | Compliant | โ |
| Family | โ | APEX-20KE |
| Device Logic Elements | โ | 8,320 |
| Number of LABs/CLBs | โ | 832 |
| Total RAM Bits | โ | 106,496 |
| Number of I/O Pins | โ | 376 |
| Number of Gates | โ | 200,000 (typical) |
| I/O Standard Support | โ | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL |
| Configuration Method | โ | Serial or Parallel PROM, JTAG (IEEE 1149.1) |
| Lead-Free / RoHS | โ | Compliant (per DigiKey listing) |