EP20K200EQC240-1 vs EP20K160EQC240-2 Comparison
Detailed side-by-side comparison of EP20K200EQC240-1 by Intel and EP20K160EQC240-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K160EQC240-2
EP20K160EQC240-2 - APEX 20KE 160K Gates FPGA | Intel | QFP-240
EP20K160EQC240-2 ObsoleteSpecification Comparison
| Parameter | EP20K200EQC240-1 | EP20K160EQC240-2 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $108.50 |
| Product Type | FPGA (Field Programmable Gate Array) | β |
| FPGA Family | APEX 20KE | β |
| Logic Elements | 8,320 | β |
| Total RAM Bits | 106,496 | β |
| Maximum User I/O | 168 | β |
| Number of Terminals | 240 | β |
| Package | 240-BFQFP (S-PQFP-G240) | PQFP-240 (QFP-240, FQFP) |
| Package Body Size | 32 mm x 32 mm | β |
| Terminal Pitch | 0.5 mm | β |
| Terminal Form | Gull wing | β |
| Package Shape | Square | β |
| Speed Grade | -1 | -2 |
| Logic Family | CMOS | CMOS |
| Propagation Delay | 2.5 ns | 1.55 ns |
| Mounting Type | Surface Mount | Surface Mount (Gull Wing) |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | β |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | β |
| Operating Temperature | [DATA_NEEDED: temperature grade] | 0 C to 85 C (Commercial) |
| Family | β | APEX 20KE |
| Typical Gates | β | 160,000 |
| Logic Elements (LEs) | β | 6,400 |
| Embedded System Blocks (ESBs) | β | 64 |
| Maximum Embedded Memory | β | 56 Kbits (approx. 7 Kbytes usable) |
| Maximum User I/O (this package) | β | 175 |
| Maximum User I/O (largest package) | β | 271 |
| PLLs | β | 4 |
| Internal Frequency (max) | β | 160 MHz |
| Process Technology | β | 0.18-micron SRAM CMOS |
| Pin Count | β | 240 |
| Supply Voltage (core) | β | [DATA_NEEDED: core VCC value] |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS |
| Configuration Modes | β | Passive Serial, Passive Parallel Synchronous, JTAG |
| JTAG Support | β | IEEE Std. 1149.1 boundary-scan |
| RoHS Status | β | Non-compliant (original Altera-era PQFP) |
| MultiCore Architecture | β | Yes (Logic + ESB + I/O) |
| 5.0 V Tolerance | β | Achievable with external resistor |