EP20K400CB652I7 vs EP20K400CB652C9ES Comparison
Detailed side-by-side comparison of EP20K400CB652I7 by Altera and EP20K400CB652C9ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CB652I7 | EP20K400CB652C9ES |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $149.50 | $195.00 |
| Family | APEX 20KC | APEX 20KC |
| Device Family | Field-Programmable Gate Array (FPGA) | β |
| Typical Gates | 400,000 | β |
| Logic Elements (LEs) | 16,640 | β |
| Maximum Operating Frequency | 375.94 MHz | 250 MHz |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS |
| Core Supply Voltage | 1.8 V | β |
| I/O Supply Voltage | 1.8 V / 3.3 V | β |
| Package | BGA-652 (652-ball) | β |
| Package Code (JESD-30) | S-PBGA-B652 | β |
| Terminal Form | Ball | β |
| Package Shape | Square | β |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O] | β |
| Embedded Memory | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM | β |
| Configuration Method | SRAM + JTAG (ISP) | β |
| Speed Grade | 7 | β |
| Temperature Grade | Industrial (-40 Β°C to +100 Β°C) | β |
| RoHS Status | Non-compliant (JESD-609 e0, contains lead) | [DATA_NEEDED: RoHS status] |
| Manufacturer Status | Obsolete (Intel/Altera legacy FPGA) | β |
| Series | β | APEX 20KC |
| Logic Elements / Cells | β | 16640 |
| Total System Gates | β | 400000 |
| Embedded Memory (Bits) | β | 212992 |
| Number of User I/O | β | 488 |
| Number of LABs/CLBs | β | [DATA_NEEDED: LAB count] |
| Number of Logic Array Blocks | β | 1040 |
| Core Voltage | β | 1.8 V |
| Operating Temperature Range | β | 0Β°C to +85Β°C (Commercial) |
| Mounting Type | β | Surface Mount |
| Package / Case | β | 652-BGA |
| MSL Level | β | 3 (168 Hours) |
| Packaging | β | Tray |
| Programmability Type | β | In-system programmable (SRAM-based) |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL |
| JTAG (IEEE 1149.1) | β | Yes |
| PLL | β | Yes (4-phase) |