EP20K400GC655-1X vs EP20K400GI655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-1X by Altera and EP20K400GI655-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400GC655-1X
EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera
EP20K400GC655-1X ObsoleteAltera
EP20K400GI655-1
EP20K400GI655-1 - 400K Gate APEX 20K FPGA | Altera | 655-BGA
EP20K400GI655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-1X | EP20K400GI655-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $193.04 | $195.00 |
| Product Family | Altera APEX 20K | β |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Technology | CMOS | CMOS, SRAM-based |
| Gate Count | 400K gates | β |
| Logic Elements | 16640 cells | 16640 |
| Maximum System Frequency | 250 MHz | β |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Core Supply Voltage | 2.5 V | β |
| I/O Supply Voltage | 2.5 V / 3.3 V | β |
| Number of User I/O | 496 | β |
| Number of Dedicated Inputs | 6 | β |
| Number of Terminals | 655 | β |
| Package Type | CPGA-655 (Ceramic Pin Grid Array) | Ceramic Pin Grid Array (CPGA-655) |
| Package Body Material | Ceramic | β |
| Process Technology | 0.22 um | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| Embedded RAM Bits | [DATA_NEEDED: embedded RAM bits] | β |
| RoHS Status | unknown | Compliant |
| Family | β | APEX 20K |
| Device Series | β | EP20K400 |
| Typical Gates | β | 400000 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 4 |
| Total Terminals | β | 655 |
| JESD-30 Package Code | β | S-CPGA-P655 |
| Operating Temperature | β | -40C to +85C (Industrial) |
| Moisture Sensitivity Level | β | MSL 1 |
| Peak Reflow Temperature | β | 220 C |
| Programmability | β | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | β | 0.18 micrometer CMOS |