EP20K400GC655-3X vs EP20K400GC655-3 Comparison
Detailed side-by-side comparison of EP20K400GC655-3X by Altera and EP20K400GC655-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-3X | EP20K400GC655-3 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $65.00 | $310.00 |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) | APEX 20K |
| Manufacturer | Altera (now Intel FPGA) | Intel (formerly Altera) |
| Logic Elements / Cells | 16,640 | β |
| System Gates | 400,000 | β |
| Total RAM Bits | 212,992 bits | 212992 |
| Maximum Internal Frequency | 167 MHz (speed grade -3) | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 um CMOS |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | β |
| I/O Supply Voltage (VCCIO) | 2.5 V (LVDS support per APEX 20KE datasheet) | β |
| Package / Case | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) | 655-BCPGA |
| Mounting Type | Through-Hole (CPGA, ceramic) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Speed Grade | -3 (fastest) | -3 (slowest grade in family) |
| Suffix Code | -X (extended / ceramic CPGA variant) | β |
| I/O Count | [DATA_NEEDED: max user I/O] | β |
| JTAG / Boundary Scan | IEEE 1149.1 (per APEX 20K family) | β |
| RoHS Status | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] | [DATA_NEEDED: rohs status] |
| Logic Elements | β | 16640 |
| Number of Gates | β | 400000 |
| Supply Voltage - Core | β | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | β | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | β | 167 MHz (per FPGAkey) |
| Supplier Device Package | β | 655-CPGA (62.48 x 62.48 mm) |
| Propagation Delay (tPD) | β | 3.6 ns (per Microchip USA listing) |
| JTAG Support | β | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | β | Passive Serial, Passive Parallel Sync/Async, Active Serial |