EP20K400GC655-3X vs EP20K400GI655-1X Comparison

Detailed side-by-side comparison of EP20K400GC655-3X by Altera and EP20K400GI655-1X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400GC655-3X EP20K400GI655-1X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $65.00 $160.00
Series APEX-20KC β€”
Family APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) APEX 20K
Manufacturer Altera (now Intel FPGA) β€”
Logic Elements / Cells 16,640 β€”
System Gates 400,000 β€”
Total RAM Bits 212,992 bits β€”
Maximum Internal Frequency 167 MHz (speed grade -3) β€”
Process Technology 0.22 Β΅m CMOS CMOS, SRAM-based configuration
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V β€”
I/O Supply Voltage (VCCIO) 2.5 V (LVDS support per APEX 20KE datasheet) β€”
Package / Case 655-BCPGA (CPGA655, 62.48 x 62.48 mm) β€”
Mounting Type Through-Hole (CPGA, ceramic) Through-Hole (PGA)
Operating Temperature [DATA_NEEDED: operating temperature range] -40 C to +85 C (industrial)
Speed Grade -3 (fastest) -1
Suffix Code -X (extended / ceramic CPGA variant) β€”
I/O Count [DATA_NEEDED: max user I/O] β€”
JTAG / Boundary Scan IEEE 1149.1 (per APEX 20K family) β€”
RoHS Status [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] Compliant
Device β€” EP20K400
Logic Elements β€” 16640
Number of Terminals β€” 655
User I/O Lines β€” 502
Dedicated Inputs β€” 4
Package Type β€” Ceramic Pin Grid Array (CPGA)
Package Code (JESD-30) β€” S-CPGA-P655
Package Equivalence Code β€” SPGA655,47X47
Package Body Material β€” CERAMIC (metal-sealed co-fired)
Propagation Delay β€” 2.5 ns (typical for -1 grade)
Moisture Sensitivity Level (MSL) β€” 1
Peak Reflow Temperature β€” 220 C

Datasheets & Resources

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