EP20K400GI655-1 vs EP20K400GI655-1X Comparison
Detailed side-by-side comparison of EP20K400GI655-1 by Altera and EP20K400GI655-1X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400GI655-1
EP20K400GI655-1 - 400K Gate APEX 20K FPGA | Altera | 655-BGA
EP20K400GI655-1 ObsoleteAltera
EP20K400GI655-1X
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoleteSpecification Comparison
| Parameter | EP20K400GI655-1 | EP20K400GI655-1X |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $160.00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | β |
| Technology | CMOS, SRAM-based | β |
| Logic Elements | 16640 | 16640 |
| Typical Gates | 400000 | β |
| Maximum User I/O | 502 | β |
| Dedicated Inputs | 4 | 4 |
| Total Terminals | 655 | β |
| Propagation Delay | 2.5 ns | 2.5 ns (typical for -1 grade) |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | Ceramic Pin Grid Array (CPGA) |
| JESD-30 Package Code | S-CPGA-P655 | β |
| Operating Temperature | -40C to +85C (Industrial) | -40 C to +85 C (industrial) |
| Moisture Sensitivity Level | MSL 1 | β |
| Peak Reflow Temperature | 220 C | 220 C |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | β |
| Process Node | 0.18 micrometer CMOS | β |
| RoHS Status | Compliant | Compliant |
| Device | β | EP20K400 |
| Number of Terminals | β | 655 |
| User I/O Lines | β | 502 |
| Package Code (JESD-30) | β | S-CPGA-P655 |
| Package Equivalence Code | β | SPGA655,47X47 |
| Package Body Material | β | CERAMIC (metal-sealed co-fired) |
| Speed Grade | β | -1 |
| Process Technology | β | CMOS, SRAM-based configuration |
| Moisture Sensitivity Level (MSL) | β | 1 |
| Mounting Type | β | Through-Hole (PGA) |