EP20K400GI655-1 vs EP20K400GI655-2 Comparison

Detailed side-by-side comparison of EP20K400GI655-1 by Altera and EP20K400GI655-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400GI655-1 EP20K400GI655-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $195.00 $175.00
Family APEX 20K β€”
Device Series EP20K400 β€”
Technology CMOS, SRAM-based CMOS SRAM
Logic Elements 16640 β€”
Typical Gates 400000 β€”
Maximum User I/O 502 496
Dedicated Inputs 4 6
Total Terminals 655 β€”
Propagation Delay 2.5 ns 3.1 ns (typical)
Package Type Ceramic Pin Grid Array (CPGA-655) β€”
JESD-30 Package Code S-CPGA-P655 β€”
Operating Temperature -40C to +85C (Industrial) -40C to +85C (industrial)
Moisture Sensitivity Level MSL 1 1 (per Altera family)
Peak Reflow Temperature 220 C β€”
Programmability In-system, JTAG boundary-scan (IEEE 1149.1) β€”
Process Node 0.18 micrometer CMOS β€”
RoHS Status Compliant [DATA_NEEDED: RoHS status]
Manufacturer β€” Altera Corporation
Series β€” APEX 20K (EP20K400)
Device Type β€” Field Programmable Gate Array (FPGA)
Typical Gate Count β€” 400,000 gates
Logic Elements (LE) β€” 16,640
Number of Terminals β€” 655
Package β€” SPGA-655 (47 mm x 47 mm)
Nominal Supply Voltage β€” 2.5 V
Supply Voltage Range β€” 2.375 V to 2.625 V
Mounting Type β€” Through-Hole / Socket
Configuration Method β€” JTAG, Passive Serial, Passive Parallel
I/O Standards Supported β€” LVTTL, LVCMOS, PCI, GTL+
Embedded Memory β€” Embedded System Blocks (ESBs)
Lifecycle Status β€” Obsolete (legacy Altera APEX 20K family)

Datasheets & Resources

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