EP20K400GI655-1X vs EP20K400GI655-1 Comparison
Detailed side-by-side comparison of EP20K400GI655-1X by Altera and EP20K400GI655-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoleteSpecification Comparison
| Parameter | EP20K400GI655-1X | EP20K400GI655-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $160.00 | $195.00 |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | β |
| Logic Elements | 16640 | 16640 |
| Number of Terminals | 655 | β |
| User I/O Lines | 502 | β |
| Dedicated Inputs | 4 | 4 |
| Package Type | Ceramic Pin Grid Array (CPGA) | Ceramic Pin Grid Array (CPGA-655) |
| Package Code (JESD-30) | S-CPGA-P655 | β |
| Package Equivalence Code | SPGA655,47X47 | β |
| Package Body Material | CERAMIC (metal-sealed co-fired) | β |
| Speed Grade | -1 | β |
| Propagation Delay | 2.5 ns (typical for -1 grade) | 2.5 ns |
| Process Technology | CMOS, SRAM-based configuration | β |
| Moisture Sensitivity Level (MSL) | 1 | β |
| Peak Reflow Temperature | 220 C | 220 C |
| Operating Temperature | -40 C to +85 C (industrial) | -40C to +85C (Industrial) |
| Mounting Type | Through-Hole (PGA) | β |
| RoHS Status | Compliant | Compliant |
| Device Series | β | EP20K400 |
| Technology | β | CMOS, SRAM-based |
| Typical Gates | β | 400000 |
| Maximum User I/O | β | 502 |
| Total Terminals | β | 655 |
| JESD-30 Package Code | β | S-CPGA-P655 |
| Moisture Sensitivity Level | β | MSL 1 |
| Programmability | β | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | β | 0.18 micrometer CMOS |