EP20K400GI655-2 vs EP20K400GI655-1 Comparison
Detailed side-by-side comparison of EP20K400GI655-2 by Altera and EP20K400GI655-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-2 | EP20K400GI655-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $195.00 |
| Manufacturer | Altera Corporation | β |
| Series | APEX 20K (EP20K400) | β |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Typical Gate Count | 400,000 gates | β |
| Logic Elements (LE) | 16,640 | β |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | β |
| Package | SPGA-655 (47 mm x 47 mm) | β |
| Nominal Supply Voltage | 2.5 V | β |
| Supply Voltage Range | 2.375 V to 2.625 V | β |
| Propagation Delay | 3.1 ns (typical) | 2.5 ns |
| Technology | CMOS SRAM | CMOS, SRAM-based |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Mounting Type | Through-Hole / Socket | β |
| Moisture Sensitivity Level | 1 (per Altera family) | MSL 1 |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | β |
| Embedded Memory | Embedded System Blocks (ESBs) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Lifecycle Status | Obsolete (legacy Altera APEX 20K family) | β |
| Family | β | APEX 20K |
| Device Series | β | EP20K400 |
| Logic Elements | β | 16640 |
| Typical Gates | β | 400000 |
| Total Terminals | β | 655 |
| Package Type | β | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | β | S-CPGA-P655 |
| Peak Reflow Temperature | β | 220 C |
| Programmability | β | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | β | 0.18 micrometer CMOS |