EP20K600CB652C8N vs EP20K600CB652C9N Comparison

Detailed side-by-side comparison of EP20K600CB652C8N by Altera and EP20K600CB652C9N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C8N EP20K600CB652C9N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $115.00 $128.00
Family APEX 20KC APEX 20KC
Device Type Loadable PLD / FPGA Loadable PLD (FPGA)
System Gates 600,000 β€”
Logic Elements 24,320 cells 24,320
Embedded Memory 311,296 bits β€”
User I/O Pins 488 β€”
Dedicated Inputs 4 β€”
Outputs 480 β€”
Propagation Delay (typ.) 1.48 ns β€”
Pin-to-Pin Timing 1.78 ns β€”
Internal Frequency (typ.) 301.21 MHz β€”
Core Supply Voltage 1.8 V nominal (1.71 V to 1.89 V) 1.8 V
Process Technology 0.18 Β΅m all-layer copper-metal 0.15 micron all-layer copper CMOS
Speed Grade C8 C9 (~1.48 ns propagation delay)
Operating Temperature 0 Β°C to 85 Β°C (commercial) 0 C to 85 C (commercial)
Package 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch)
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
Architecture MultiCore LUT + Embedded System Blocks (ESB) MultiCore LUT + embedded system memory (ESB)
Pin-Compatible With APEX 20KE family β€”
RoHS Status unknown [DATA_NEEDED: rohs status]
Typical Gates β€” 600,000
Maximum User I/O β€” 488
On-chip Memory β€” Embedded system memory blocks (dual-port RAM, FIFO)
Configuration Interface β€” JTAG (IEEE 1149.1) and serial/PROM configuration
Pin/Pin Compatibility β€” Pin-compatible with APEX 20KE devices of same package
Toolchain β€” Altera/Intel Quartus II (legacy APEX support)
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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