EP20K600CB652C9N vs EP20K600CB652C8N Comparison

Detailed side-by-side comparison of EP20K600CB652C9N by Intel and EP20K600CB652C8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C9N EP20K600CB652C8N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $128.00 $115.00
Family APEX 20KC APEX 20KC
Device Type Loadable PLD (FPGA) Loadable PLD / FPGA
Typical Gates 600,000 β€”
Logic Elements 24,320 24,320 cells
Maximum User I/O 488 β€”
Package BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch
Process Technology 0.15 micron all-layer copper CMOS 0.18 Β΅m all-layer copper-metal
Core Supply Voltage 1.8 V 1.8 V nominal (1.71 V to 1.89 V)
Speed Grade C9 (~1.48 ns propagation delay) C8
Architecture MultiCore LUT + embedded system memory (ESB) MultiCore LUT + Embedded System Blocks (ESB)
On-chip Memory Embedded system memory blocks (dual-port RAM, FIFO) β€”
Configuration Interface JTAG (IEEE 1149.1) and serial/PROM configuration β€”
Operating Temperature 0 C to 85 C (commercial) 0 Β°C to 85 Β°C (commercial)
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
Pin/Pin Compatibility Pin-compatible with APEX 20KE devices of same package β€”
Toolchain Altera/Intel Quartus II (legacy APEX support) β€”
RoHS Status [DATA_NEEDED: rohs status] unknown
MSL Level [DATA_NEEDED: MSL level] β€”
System Gates β€” 600,000
Embedded Memory β€” 311,296 bits
User I/O Pins β€” 488
Dedicated Inputs β€” 4
Outputs β€” 480
Propagation Delay (typ.) β€” 1.48 ns
Pin-to-Pin Timing β€” 1.78 ns
Internal Frequency (typ.) β€” 301.21 MHz
Pin-Compatible With β€” APEX 20KE family

Datasheets & Resources

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