EP20K600CF1020C9 vs EP20K600CF33C9 Comparison
Detailed side-by-side comparison of EP20K600CF1020C9 by Intel and EP20K600CF33C9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K600CF1020C9 - APEX 20KC FPGA 600K Gates 250MHz 1020-FBGA | Intel
EP20K600CF1020C9 ObsoleteSpecification Comparison
| Parameter | EP20K600CF1020C9 | EP20K600CF33C9 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $165.00 | $171.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | β |
| System Gates | 600,000 | 600,000 (maximum) |
| Maximum Operating Frequency | 250 MHz | 250 MHz |
| Embedded Memory (ESB) | Configurable dual-port RAM / FIFO / CAM / ROM | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V | β |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | β |
| User I/O Pins | 588 | β |
| Dedicated Inputs | 4 | β |
| Total I/O Count (in/out) | 580 / 580 | β |
| Package | 1020-ball FC-FBGA (33 x 33 mm, 1.00 mm pitch) | 1020-ball FC-FBGA |
| JESD-30 Package Code | S-PBGA-B1020 | β |
| Operating Temperature | 0Β°C to 85Β°C (TJ) | β |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (33/66 MHz, 32/64-bit, 3.3 V) | β |
| External Memory Support | DDR SDRAM, ZBT SRAM | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Logic Elements / Cells | β | 24,320 |
| Maximum Clock Frequency | β | 303.03 MHz |
| Propagation Delay | β | 2.0 ns |
| Core Supply Voltage (VCCINT) | β | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | β | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Mounting Type | β | Surface Mount (BGA) |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | β | Dual-port RAM blocks (per family) |
| Programmability | β | JTAG / IEEE 1149.1 ISP, SRAM-based |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | β | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | β | LVTTL, LVCMOS, LVDS (per family datasheet) |