EP20K600CF33C7N vs EP20K600CF33C9 Comparison

Detailed side-by-side comparison of EP20K600CF33C7N by Intel and EP20K600CF33C9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF33C7N EP20K600CF33C9
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $110.00 $171.00
Series APEX-20K β€”
Family APEX 20KC APEX 20KC
Logic Elements / Cells 24320 24,320
Total Gates 600000 β€”
Total RAM Bits 311296 β€”
Number of I/O [DATA_NEEDED: number of user I/O] β€”
Number of PLLs 4 β€”
Pin-to-Pin Logic Delay (tPD) 1.48 ns β€”
Max Operating Frequency 375.94 MHz β€”
Process Technology 0.15 Β΅m CMOS 0.15 Β΅m CMOS
Core Supply Voltage (VCCINT) 1.8 V (1.71 V to 1.89 V) 1.8 V nominal (1.71 V to 1.89 V)
Supplier Device Package 1020-FBGA (33 x 33 mm) β€”
Package / Case 1020-BBGA, FCBGA β€”
Mounting Type Surface Mount Surface Mount (BGA)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Operating Temperature 0 Β°C to 85 Β°C (commercial, based on speed grade C7) β€”
System Gates β€” 600,000 (maximum)
Maximum Operating Frequency β€” 250 MHz
Maximum Clock Frequency β€” 303.03 MHz
Propagation Delay β€” 2.0 ns
User I/O β€” 588 (4 dedicated inputs + 580 general-purpose I/O)
Package β€” 1020-ball FC-FBGA
Operating Temperature Range β€” [DATA_NEEDED: operating temperature range]
Embedded RAM β€” Dual-port RAM blocks (per family)
Programmability β€” JTAG / IEEE 1149.1 ISP, SRAM-based
MSL Level β€” [DATA_NEEDED: MSL level]
Logic Block Architecture β€” MultiCore (LUT + product-term + embedded memory)
I/O Standards Supported β€” LVTTL, LVCMOS, LVDS (per family datasheet)

Datasheets & Resources

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