EP20K600CF33C9 vs EP20K600CF1020C8 Comparison
Detailed side-by-side comparison of EP20K600CF33C9 by Intel and EP20K600CF1020C8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF33C9 | EP20K600CF1020C8 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $171.00 | $92.00 |
| Family | APEX 20KC | APEX 20KC |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS |
| System Gates | 600,000 (maximum) | 600,000 |
| Logic Elements / Cells | 24,320 | 24,320 |
| Maximum Operating Frequency | 250 MHz | β |
| Maximum Clock Frequency | 303.03 MHz | β |
| Propagation Delay | 2.0 ns | β |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | β |
| User I/O | 588 (4 dedicated inputs + 580 general-purpose I/O) | β |
| Package | 1020-ball FC-FBGA | 1020-ball FC-FBGA (1.00 mm pitch) |
| Mounting Type | Surface Mount (BGA) | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| Embedded RAM | Dual-port RAM blocks (per family) | β |
| Programmability | JTAG / IEEE 1149.1 ISP, SRAM-based | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Logic Block Architecture | MultiCore (LUT + product-term + embedded memory) | β |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS (per family datasheet) | β |
| Series | β | EP20K600 |
| Embedded Memory (ESB) | β | 311 Kbit (max) |
| Core Supply Voltage | β | 1.8 V |
| I/O Supply Voltage | β | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Maximum Internal Frequency | β | 301.21 MHz (C8 speed grade) |
| User I/O Pins | β | 588 |
| Dedicated Inputs | β | 4 |
| Operating Temperature | β | 0 Β°C to +85 Β°C (commercial, "C") |
| Speed Grade | β | C8 |
| Configuration Interface | β | Serial / JTAG (IEEE 1149.1) |
| PCI Compliance | β | PCI SIG Local Bus Spec Rev 2.2, 32/64-bit, 33/66 MHz, 3.3 V |