EP20K600CF672C7N vs EP20K600CF672-1X Comparison

Detailed side-by-side comparison of EP20K600CF672C7N by Altera and EP20K600CF672-1X by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672C7N EP20K600CF672-1X
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $108.00 $95.00
Device Family APEX 20KC APEX 20KC MultiCore FPGA
Maximum System Gates 1,052,000 β€”
Typical Gates 600,000 β€”
Logic Elements / Cells 24,320 β€”
Maximum User I/O Pins 488 β€”
Total Package Pins 652 β€”
Package FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch 672-ball BGA (CF672), 1.27 mm pitch
Core Voltage 1.8 V β€”
Maximum Operating Frequency 375.94 MHz β€”
Propagation Delay 1.48 ns β€”
Process Technology 0.15 Β΅m all-layer copper-metal CMOS 0.18 um SRAM CMOS
Architecture MultiCore (LUT + Embedded System Memory) β€”
Operating Temperature 0 Β°C to +85 Β°C (Commercial) [DATA_NEEDED: industrial temp range]
Speed Grade C7 -1 (industrial speed grade, X = lead-free)
Seated Height 3.50 mm β€”
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
RoHS Status unknown Compliant (per Alibaba distributor listing: "RoHS Compliant")
Series β€” APEX 20KC
Maximum Typical Gates β€” 600,000
Logic Elements β€” 31,104 (per Altera APEX 20KC datasheet family)
Embedded System Blocks (ESBs) β€” up to 256
Embedded Memory (max bits) β€” [DATA_NEEDED: ESB RAM bits]
PLLs β€” 4
Maximum User I/O β€” [DATA_NEEDED: max user I/O count]
Configuration Method β€” SRAM, JTAG (IEEE 1149.1), EPC passive serial
Supply Voltage β€” [DATA_NEEDED: VCCINT/VCCIO]
MSL Level β€” [DATA_NEEDED: MSL rating]

Datasheets & Resources

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