EP20K600CF672I-8ES vs EP20K600CF672I7N Comparison
Detailed side-by-side comparison of EP20K600CF672I-8ES by Altera and EP20K600CF672I7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES Obsolete
Specification Comparison
| Parameter | EP20K600CF672I-8ES | EP20K600CF672I7N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $119.00 | $232.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| Typical Gates | 600,000 (ASIC-equivalent) | β |
| Embedded Memory Bits | 311,296 | β |
| Maximum User I/O Pins | 508 | 508 |
| Embedded PLLs | 4 | β |
| Core Voltage | 1.8 V | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ | β |
| Process Technology | 0.18 micron CMOS SRAM | β |
| Speed Grade | -8 (slower) | I7 (-40 Β°C to +100 Β°C industrial) |
| Operating Temperature | -40C to +100C (Industrial) | β |
| Package | 672-ball BGA (FineLine BGA, 1.27 mm pitch) | 672-ball FineLine BGA (FC-FBGA) |
| Configuration Modes | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG | β |
| In-System Programmability | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) | β |
| RoHS Status | Non-compliant (legacy Altera leaded BGA process) | [DATA_NEEDED: RoHS compliance] |
| MSL Level | [DATA_NEEDED: moisture sensitivity level] | β |
| Technology | β | 0.15 Β΅m CMOS |
| Maximum System Gates | β | 600,000 |
| Maximum Internal Frequency | β | 376 MHz |
| Embedded System Blocks (ESBs) | β | 160 |
| Total Embedded RAM (max) | β | 311,296 bits |
| Core Voltage (VCCINT) | β | 1.8 V |
| I/O Voltage (VCCIO) | β | 2.5 V / 3.3 V (MultiVolt, bank-dependent) |
| Ball Pitch | β | 1.0 mm |
| Package Body Size | β | 27 mm Γ 27 mm |
| Propagation Delay (typical) | β | 1.6 ns |
| Configuration Method | β | JTAG (IEEE 1149.1) + EPC configuration device |
| Lead-Free Finish (N suffix) | β | Yes |