EP20K600CF672I7N vs EP20K600CF672C7N Comparison
Detailed side-by-side comparison of EP20K600CF672I7N by Intel and EP20K600CF672C7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF672I7N | EP20K600CF672C7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $232.00 | $108.00 |
| Family | APEX 20KC | β |
| Technology | 0.15 Β΅m CMOS | β |
| Maximum System Gates | 600,000 | 1,052,000 |
| Logic Elements | 24,320 | β |
| Maximum User I/O Pins | 508 | 488 |
| Maximum Internal Frequency | 376 MHz | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Total Embedded RAM (max) | 311,296 bits | β |
| Core Voltage (VCCINT) | 1.8 V | β |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | β |
| Package | 672-ball FineLine BGA (FC-FBGA) | FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.0 mm | β |
| Package Body Size | 27 mm Γ 27 mm | β |
| Speed Grade | I7 (-40 Β°C to +100 Β°C industrial) | C7 |
| Propagation Delay (typical) | 1.6 ns | β |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | β |
| Lead-Free Finish (N suffix) | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Device Family | β | APEX 20KC |
| Typical Gates | β | 600,000 |
| Logic Elements / Cells | β | 24,320 |
| Total Package Pins | β | 652 |
| Core Voltage | β | 1.8 V |
| Maximum Operating Frequency | β | 375.94 MHz |
| Propagation Delay | β | 1.48 ns |
| Process Technology | β | 0.15 Β΅m all-layer copper-metal CMOS |
| Architecture | β | MultiCore (LUT + Embedded System Memory) |
| Operating Temperature | β | 0 Β°C to +85 Β°C (Commercial) |
| Seated Height | β | 3.50 mm |
| Mounting Type | β | Surface Mount (BGA) |