EP20K600CF672I7N vs EP20K600CF672I-8ES Comparison
Detailed side-by-side comparison of EP20K600CF672I7N by Intel and EP20K600CF672I-8ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES ObsoleteSpecification Comparison
| Parameter | EP20K600CF672I7N | EP20K600CF672I-8ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $232.00 | $119.00 |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 Β΅m CMOS | β |
| Maximum System Gates | 600,000 | β |
| Logic Elements | 24,320 | 24,320 |
| Maximum User I/O Pins | 508 | 508 |
| Maximum Internal Frequency | 376 MHz | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Total Embedded RAM (max) | 311,296 bits | β |
| Core Voltage (VCCINT) | 1.8 V | β |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | β |
| Package | 672-ball FineLine BGA (FC-FBGA) | 672-ball BGA (FineLine BGA, 1.27 mm pitch) |
| Ball Pitch | 1.0 mm | β |
| Package Body Size | 27 mm Γ 27 mm | β |
| Speed Grade | I7 (-40 Β°C to +100 Β°C industrial) | -8 (slower) |
| Propagation Delay (typical) | 1.6 ns | β |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | β |
| Lead-Free Finish (N suffix) | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy Altera leaded BGA process) |
| Typical Gates | β | 600,000 (ASIC-equivalent) |
| Embedded Memory Bits | β | 311,296 |
| Embedded PLLs | β | 4 |
| Core Voltage | β | 1.8 V |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Process Technology | β | 0.18 micron CMOS SRAM |
| Operating Temperature | β | -40C to +100C (Industrial) |
| Configuration Modes | β | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG |
| In-System Programmability | β | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) |
| MSL Level | β | [DATA_NEEDED: moisture sensitivity level] |