EP20K600CF672I7N vs EP20K600CF672I7 Comparison
Detailed side-by-side comparison of EP20K600CF672I7N by Intel and EP20K600CF672I7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF672I7N | EP20K600CF672I7 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $232.00 | $220.00 |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 Β΅m CMOS | β |
| Maximum System Gates | 600,000 | β |
| Logic Elements | 24,320 | β |
| Maximum User I/O Pins | 508 | β |
| Maximum Internal Frequency | 376 MHz | 375.94 MHz |
| Embedded System Blocks (ESBs) | 160 | β |
| Total Embedded RAM (max) | 311,296 bits | β |
| Core Voltage (VCCINT) | 1.8 V | β |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | β |
| Package | 672-ball FineLine BGA (FC-FBGA) | 672-ball FineLine BGA (FC-FBGA, 27Γ27 mm) |
| Ball Pitch | 1.0 mm | 1.00 mm |
| Package Body Size | 27 mm Γ 27 mm | β |
| Speed Grade | I7 (-40 Β°C to +100 Β°C industrial) | -7 |
| Propagation Delay (typical) | 1.6 ns | β |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | β |
| Lead-Free Finish (N suffix) | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Maximum Logic Elements | β | 24,320 cells |
| System Gates | β | 600,000 |
| Maximum User I/O | β | 508 |
| Process Technology | β | 0.15 Β΅m CMOS |
| Core Supply Voltage (VCCINT) | β | 1.8 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V (LVTTL/LVCMOS compatible) |
| Operating Temperature | β | -40 Β°C to +100 Β°C (industrial, I-suffix) |
| Embedded System Blocks | β | Yes (dual-port RAM / CAM) |
| Configuration Interface | β | IEEE 1149.1 JTAG, passive serial, fast passive parallel |
| Mounting Type | β | Surface Mount (BGA) |