EP20K600CF672I7N vs EP20K600CF672I9N Comparison
Detailed side-by-side comparison of EP20K600CF672I7N by Intel and EP20K600CF672I9N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF672I7N | EP20K600CF672I9N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $232.00 | $120.00 |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 Β΅m CMOS | β |
| Maximum System Gates | 600,000 | β |
| Logic Elements | 24,320 | 24,320 cells |
| Maximum User I/O Pins | 508 | β |
| Maximum Internal Frequency | 376 MHz | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Total Embedded RAM (max) | 311,296 bits | β |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | [DATA_NEEDED: VCCIO range] |
| Package | 672-ball FineLine BGA (FC-FBGA) | 672-ball FC-FBGA |
| Ball Pitch | 1.0 mm | β |
| Package Body Size | 27 mm Γ 27 mm | β |
| Speed Grade | I7 (-40 Β°C to +100 Β°C industrial) | β |
| Propagation Delay (typical) | 1.6 ns | β |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | β |
| Lead-Free Finish (N suffix) | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Typical Gates | β | 600,000 |
| Maximum Frequency | β | 250 MHz |
| Process Technology | β | 0.15 Β΅m CMOS |
| Embedded Memory | β | 311,040 bits (approx. 38 KB) |
| PLL Count | β | [DATA_NEEDED: PLL count] |
| User I/O Pins | β | [DATA_NEEDED: max user I/O] |
| Configuration Mode | β | JTAG / Serial / Parallel |
| Programming Interface | β | IEEE 1149.1 JTAG |
| Operating Temperature | β | -40 Β°C to +85 Β°C (industrial) |