EP20K60EFC324-1 vs EP20K100EFC324-1N Comparison

Detailed side-by-side comparison of EP20K60EFC324-1 by Altera and EP20K100EFC324-1N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K60EFC324-1 EP20K100EFC324-1N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $76.50 $108.00
Series APEX-20KEยฎ โ€”
Family APEX 20K (Enhanced) APEX-20KE
Logic Elements / Cells 2560 โ€”
Total Gates 60,000 (typical) โ€”
Total RAM Bits 32768 โ€”
Number of I/O 196 โ€”
Number of Logic Blocks/Elements 2560 โ€”
Core Supply Voltage 1.71 V to 1.89 V (1.8 V nominal) โ€”
Process Technology 0.22 ยตm CMOS 0.15 ยตm all-layer copper CMOS
Maximum Operating Frequency 250 MHz โ€”
Speed Grade -1 โ€”
Package / Case 324-FBGA (FineLine BGA, 19x19 mm) โ€”
Supplier Device Package 324-FBGA (19x19) โ€”
Mounting Type Surface Mount โ€”
Operating Temperature 0 ยฐC to +85 ยฐC (commercial) 0 C to 85 C
RoHS Status Non-compliant (legacy) โ€”
Lead Free Status Contains lead (legacy) โ€”
Device Type โ€” FPGA (Field Programmable Gate Array)
Logic Elements (LEs) โ€” 4160
Typical Gates โ€” 100,000
Maximum User I/O โ€” 246
Embedded System Blocks (ESBs) โ€” 53248 bits
Package โ€” 324-BGA (FineLine BGA)
Propagation Delay โ€” 1.6 ns
Internal Operating Frequency โ€” 250 MHz
Core Voltage โ€” 1.8 V
I/O Standard Support โ€” LVDS, SSTL, HSTL, LVTTL, LVCMOS
JTAG Support โ€” IEEE 1149.1 boundary-scan
Programming Technology โ€” SRAM-based (volatile, requires configuration device)
MultiVolt I/O โ€” 1.8 V core with 3.3 V / 5.0 V I/O support

Datasheets & Resources

Browse All Products Create BOM Request Quote