EP20K60EFI144-2X vs EP20K60ETC144-2N Comparison
Detailed side-by-side comparison of EP20K60EFI144-2X by Altera and EP20K60ETC144-2N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K60EFI144-2X
EP20K60EFI144-2X - APEX 20KE FPGA 60K Gates 144-FBGA | Altera
EP20K60EFI144-2X NrndIntel
EP20K60ETC144-2N
EP20K60ETC144-2N - APEX-20KE 60K FPGA, 92 I/O, 144-TQFP | Intel
EP20K60ETC144-2N ObsoleteSpecification Comparison
| Parameter | EP20K60EFI144-2X | EP20K60ETC144-2N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $65.00 | $65.00 |
| Device Family | APEX 20KE | β |
| Typical Gates | 60,000 | 60,000 |
| Logic Elements | 2,560 | 2,560 |
| Maximum Operating Frequency | 200 MHz | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V (range 1.71 V to 1.89 V) | β |
| Propagation Delay (tpd) | 2.41 ns | β |
| User I/O Pins | 93 | β |
| Dedicated Inputs | 4 | β |
| Total Terminals | 144 | β |
| Package Type | FBGA-144 (FineLine BGA, LBGA) | β |
| Package Code | LBGA | β |
| Terminal Form | Ball | β |
| Architecture | MultiCore (LUT + product-term + embedded memory) | β |
| I/O Standard Support | LVDS, 1.8 V I/O | β |
| Speed Grade | -2 (industrial, -2X suffix) | -2 |
| Operating Temperature | -40 Β°C to +85 Β°C | 0 Β°C to 85 Β°C (commercial) |
| Configuration Interface | JTAG (IEEE 1149.1) / serial PROM / parallel PROM | β |
| Moisture Sensitivity Level (MSL) | 3 | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Family | β | APEX-20KE |
| Embedded Memory (ESB) | β | 32,768 bits (32 Kbits) |
| User I/Os | β | 92 |
| Core Voltage (VCCINT) | β | 1.71 V to 1.89 V (1.8 V nominal) |
| Internal Frequency (max) | β | 160 MHz |
| Propagation Delay | β | 1.72 ns |
| Package | β | 144-pin TQFP (20 Γ 20 mm, 0.5 mm pitch) |
| Logic Family | β | CMOS |
| JTAG Support | β | IEEE 1149.1 boundary-scan |